1. Field
Exemplary embodiments of the present invention relate generally to a semiconductor design technology and, more particularly, to a semiconductor device capable of controlling a read operation and a precharge operation of a fuse array, and a method for operating the semiconductor device.
2. Description of the Related Art
In general, a semiconductor device such as a double data rate synchronous dynamic random access memory (DDR SDRAM) includes a fuse circuit. The fuse circuit may store various pieces of information to be used for the circuit operation of the semiconductor device. For example, the fuse circuit may store various result values obtained through a test operation on the semiconductor device, and the semiconductor device uses the result values stored in the fuse circuit when performing a circuit operation. Accordingly, even though the characteristics of new semiconductor memory devices are slightly different from each other, all the semiconductor memory devices may perform substantially the same operation based on information stored in the fuse circuit. Consequently, the fuse circuit serves as the basis for providing an environment in which a number of semiconductor devices may perform substantially the same operation.
Hereinafter, a brief description of a typical a fuse circuit is provided.
The fuse circuit includes a plurality of fuses in which various pieces of information are stored. For the sake of convenience in description, a series of operations for storing particular information in a fuse is referred to as a “program operation”. A method for programming particular information in a fuse may be classified as a physical or an electrical method.
A physical method includes cutting a fuse by blowing the fuse using a laser beam, and the like, according to information to be programmed. The fuse used in the physical method is referred to as a physical fuse. Since the laser beam is used to cut the connection state of the fuse, the fuse is also referred to as a laser blowing fuse. The physical fuse may be programmed only in a wafer stage before a semiconductor device is packaged. Hence, the physical fuse may not be programmed after the wafer stage.
The electrical method includes changing the connection state of a fuse by applying an overcurrent to the fuse based on information to be programmed. The fuse used in the electrical method is referred to as an electrical fuse. The electrical fuse may be classified into anti-type fuses and blowing type fuses. When being programmed, the anti-type fuse changes from an initial open state to a short state and the blowing type fuse changes from an initial short state to an open state. Such electrical fuse is advantageous over the physical fuse in that the program operations are possible after the wafer state, that is, even in a package state. Accordingly, recent trends have shown that the electrical method is preferred to the physical method in designing a semiconductor device.
A semiconductor device is designed to perform various operations required by consumers. Performing various operations means an increase in the number of fuses for storing the information for the various operations. Recently substantial research has been targeted to improved technologies for efficiently managing a larger number of fuses. One such technology is the fuse array circuit technology.
FIG. 1 illustrates a conventional fuse array circuit. Referring to FIG. 1, the fuse array circuit has a plurality of fuse memory cells disposed in an array form. Hereinafter, for the sake of convenience in description, one fuse cell 110 of the fuse memory cells is described.
The fuse cell 110 includes a fuse F and a selection transistor TR. The fuse F is coupled to a program word line WLP1 and the selection transistor TR is coupled to a read word line WLR1. The fuse F stores information and may be designed using various types of fuses, as described above.
Hereinafter, a simple read operation of the fuse array circuit will be described. For convenience, it is assumed that the fuse array circuit stores predetermined information through a program operation.
In a read operation for outputting information programmed in the fuse F, a predetermined constant voltage is applied to the program word line WLP1 and the read word line WLR1. Then, a bit line BL1 may have a voltage level corresponding to the information programmed in the fuse F. That is, when the fuse F is in an open state, the bit line BL1 substantially maintains a precharged voltage, and when the fuse F is in a short state, since the predetermined voltage is transferred to the bit line BL1 via the fuse F and the selection transistor TR, the bit line BL1 is driven to a voltage level corresponding to the predetermined voltage. Although not illustrated in the drawing, a circuit for detecting and outputting the voltage level of the bit line BL1 in the read operation is coupled to the bit line BL1. As a result, the information programed in the fuse F is outputted through the bit line BL1 so that the semiconductor device performs a predetermined circuit operation using the outputted information.
As described above, the fuse F may enter the open state or the short state through the program operation. Ideally, a fuse F in the open state and a fuse F in the short state should have constant resistance values respectively. However actual resistance values of fuses F may be slightly different from each other. Accordingly, sensing (or detecting) operation timing may be set based on an assumption that the fuses F have the worst possible resistance value.
Furthermore, as described above, in a read operation of the fuse F, a predetermined constant voltage is applied to the program word line WLP1 and the read word line WLR1. In general, after the predetermined constant voltage is applied to the program word line WLP1 and the read word line WLR1, a read operation and a precharge operation may be performed together. However, when the read operation is performed together with the precharge operation, a drain-source voltage Vds of the selection transistor TR may greatly increase. In this case, a corresponding transistor may malfunction because of the negative influence on the reliability of the transistor.